mcm-binutils-2.44-merged.diff (54937B)
1 diff -ru --no-dereference --show-c-function binutils-2.44/bfd/archures.c binutils-2.44-0004-s390x-pie-symbol-binding/bfd/archures.c 2 --- a/bfd/archures.c 2025-02-02 00:00:00.000000000 +0000 3 +++ b/bfd/archures.c 2025-11-30 01:43:04.000000000 +0000 4 @@ -288,6 +288,8 @@ DESCRIPTION 5 .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 6 .#define bfd_mach_sh2a_or_sh4 0x2a3 7 .#define bfd_mach_sh2a_or_sh3e 0x2a4 8 +.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 9 +.#define bfd_mach_shj2 0x2c 10 .#define bfd_mach_sh2e 0x2e 11 .#define bfd_mach_sh3 0x30 12 .#define bfd_mach_sh3_nommu 0x31 13 diff -ru --no-dereference --show-c-function binutils-2.44/bfd/bfd-in2.h binutils-2.44-0004-s390x-pie-symbol-binding/bfd/bfd-in2.h 14 --- a/bfd/bfd-in2.h 2025-02-02 00:00:00.000000000 +0000 15 +++ b/bfd/bfd-in2.h 2025-11-30 01:43:04.000000000 +0000 16 @@ -1556,6 +1556,8 @@ enum bfd_architecture 17 #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 18 #define bfd_mach_sh2a_or_sh4 0x2a3 19 #define bfd_mach_sh2a_or_sh3e 0x2a4 20 +#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 21 +#define bfd_mach_shj2 0x2c 22 #define bfd_mach_sh2e 0x2e 23 #define bfd_mach_sh3 0x30 24 #define bfd_mach_sh3_nommu 0x31 25 diff -ru --no-dereference --show-c-function binutils-2.44/bfd/cpu-sh.c binutils-2.44-0004-s390x-pie-symbol-binding/bfd/cpu-sh.c 26 --- a/bfd/cpu-sh.c 2025-02-02 00:00:00.000000000 +0000 27 +++ b/bfd/cpu-sh.c 2025-11-30 01:43:04.000000000 +0000 28 @@ -63,7 +63,9 @@ static const bfd_arch_info_type arch_inf 29 N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", false, arch_info_struct + 16), 30 N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", false, arch_info_struct + 17), 31 N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", false, arch_info_struct + 18), 32 - N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, NULL) 33 + N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, arch_info_struct + 19), 34 + N (bfd_mach_shj2, "j2", false, arch_info_struct + 20), 35 + N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-or-sh3e-or-j2", false, NULL), 36 }; 37 38 const bfd_arch_info_type bfd_sh_arch = 39 @@ -99,6 +101,8 @@ static struct { unsigned long bfd_mach, 40 { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, 41 { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, 42 { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, 43 + { bfd_mach_shj2, arch_shj2, arch_shj2_up }, 44 + { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, 45 { 0, 0, 0 } /* Terminator. */ 46 }; 47 48 diff -ru --no-dereference --show-c-function binutils-2.44/bfd/elf32-sh.c binutils-2.44-0004-s390x-pie-symbol-binding/bfd/elf32-sh.c 49 --- a/bfd/elf32-sh.c 2025-02-02 00:00:00.000000000 +0000 50 +++ b/bfd/elf32-sh.c 2025-11-30 01:43:12.000000000 +0000 51 @@ -64,7 +64,7 @@ static bfd_vma tpoff 52 not. If the symbol is protected, we want the local address, but 53 its function descriptor must be assigned by the dynamic linker. */ 54 #define SYMBOL_FUNCDESC_LOCAL(INFO, H) \ 55 - (SYMBOL_REFERENCES_LOCAL (INFO, H) \ 56 + (!(H) || (H)->dynindx < 0 || (H)->forced_local \ 57 || ! elf_hash_table (INFO)->dynamic_sections_created) 58 59 #define SH_PARTIAL32 true 60 @@ -4278,20 +4278,6 @@ sh_elf_relocate_section (bfd *output_bfd 61 /* Undefined weak symbol which will not be dynamically 62 resolved later; leave it at zero. */ 63 goto funcdesc_leave_zero; 64 - else if (SYMBOL_CALLS_LOCAL (info, h) 65 - && ! SYMBOL_FUNCDESC_LOCAL (info, h)) 66 - { 67 - /* If the symbol needs a non-local function descriptor 68 - but binds locally (i.e., its visibility is 69 - protected), emit a dynamic relocation decayed to 70 - section+offset. This is an optimization; the dynamic 71 - linker would resolve our function descriptor request 72 - to our copy of the function anyway. */ 73 - dynindx = elf_section_data (h->root.u.def.section 74 - ->output_section)->dynindx; 75 - relocation += h->root.u.def.section->output_offset 76 - + h->root.u.def.value; 77 - } 78 else if (! SYMBOL_FUNCDESC_LOCAL (info, h)) 79 { 80 /* If the symbol is dynamic and there will be dynamic 81 diff -ru --no-dereference --show-c-function binutils-2.44/bfd/elf64-s390.c binutils-2.44-0004-s390x-pie-symbol-binding/bfd/elf64-s390.c 82 --- a/bfd/elf64-s390.c 2025-02-02 00:00:00.000000000 +0000 83 +++ b/bfd/elf64-s390.c 2025-11-30 01:43:27.371117049 +0000 84 @@ -2691,7 +2691,7 @@ elf_s390_relocate_section (bfd *output_b 85 || r_type == R_390_PC32DBL 86 || r_type == R_390_PC64 87 || !bfd_link_pic (info) 88 - || !SYMBOLIC_BIND (info, h) 89 + || !(bfd_link_pie (info) || SYMBOLIC_BIND (info, h)) 90 || !h->def_regular)) 91 { 92 outrel.r_info = ELF64_R_INFO (h->dynindx, r_type); 93 diff -ru --no-dereference --show-c-function binutils-2.44/bfd/elfnn-riscv.c binutils-2.44-0004-s390x-pie-symbol-binding/bfd/elfnn-riscv.c 94 --- a/bfd/elfnn-riscv.c 2025-02-02 00:00:00.000000000 +0000 95 +++ b/bfd/elfnn-riscv.c 2025-11-30 01:43:20.000000000 +0000 96 @@ -99,7 +99,7 @@ 97 ((H) != NULL \ 98 && (H)->dynindx != -1 \ 99 && (!bfd_link_pic (INFO) \ 100 - || !SYMBOLIC_BIND ((INFO), (H)) \ 101 + || !(bfd_link_pie ((INFO)) || SYMBOLIC_BIND ((INFO), (H))) \ 102 || !(H)->def_regular)) 103 104 /* True if this is actually a static link, or it is a -Bsymbolic link 105 diff -ru --no-dereference --show-c-function binutils-2.44/binutils/readelf.c binutils-2.44-0004-s390x-pie-symbol-binding/binutils/readelf.c 106 --- a/binutils/readelf.c 2025-02-02 00:00:00.000000000 +0000 107 +++ b/binutils/readelf.c 2025-11-30 01:43:04.000000000 +0000 108 @@ -4687,6 +4687,12 @@ decode_SH_machine_flags (char *out, unsi 109 case EF_SH2A_SH3E: 110 out = stpcpy (out, ", sh2a-or-sh3e"); 111 break; 112 + case EF_SHJ2: 113 + out = stpcpy (out, ", j2"); 114 + break; 115 + case EF_SH2A_SH3_SHJ2: 116 + out = stpcpy (out, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); 117 + break; 118 default: 119 out = stpcpy (out, _(", unknown ISA")); 120 break; 121 diff -ru --no-dereference --show-c-function binutils-2.44/gas/config/tc-sh.c binutils-2.44-0004-s390x-pie-symbol-binding/gas/config/tc-sh.c 122 --- a/gas/config/tc-sh.c 2025-02-02 00:00:00.000000000 +0000 123 +++ b/gas/config/tc-sh.c 2025-11-30 01:43:04.000000000 +0000 124 @@ -1251,6 +1251,8 @@ get_operands (sh_opcode_info *info, char 125 if (*ptr == ',') 126 ptr++; 127 get_operand (&ptr, operand + 2); 128 + if (strcmp (info->name,"cas") == 0) 129 + operand[2].type = A_IND_0; 130 } 131 } 132 } 133 @@ -1775,7 +1777,10 @@ get_specific (sh_opcode_info *opcode, sh 134 goto fail; 135 reg_m = 4; 136 break; 137 - 138 + case A_IND_0: 139 + if (user->reg != 0) 140 + goto fail; 141 + break; 142 default: 143 printf (_("unhandled %d\n"), arg); 144 goto fail; 145 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 146 --- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2025-02-02 00:00:00.000000000 +0000 147 +++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2025-11-30 01:43:04.000000000 +0000 148 @@ -12,8 +12,6 @@ 149 sh2a_nofpu_or_sh3_nommu: 150 ! Instructions introduced into sh2a-nofpu-or-sh3-nommu 151 pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} 152 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 153 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 154 155 ! Instructions inherited from ancestors: sh sh2 156 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 157 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 158 --- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2025-02-02 00:00:00.000000000 +0000 159 +++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2025-11-30 01:43:04.000000000 +0000 160 @@ -12,7 +12,7 @@ 161 sh2a_nofpu_or_sh4_nommu_nofpu: 162 ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu 163 164 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu 165 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu 166 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 167 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 168 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 169 @@ -119,8 +119,8 @@ sh2a_nofpu_or_sh4_nommu_nofpu: 170 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 171 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 172 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 173 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 174 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 175 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 176 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 177 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 178 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 179 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 180 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 181 --- a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2025-02-02 00:00:00.000000000 +0000 182 +++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2025-11-30 01:43:04.000000000 +0000 183 @@ -64,7 +64,7 @@ sh2a_nofpu: 184 movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} 185 movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} 186 187 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu 188 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu 189 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 190 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 191 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 192 @@ -171,8 +171,8 @@ sh2a_nofpu: 193 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 194 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 195 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 196 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 197 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 198 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 199 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 200 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 201 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 202 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 203 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 204 --- a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2025-02-02 00:00:00.000000000 +0000 205 +++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2025-11-30 01:43:04.000000000 +0000 206 @@ -13,7 +13,7 @@ sh2a_or_sh3e: 207 ! Instructions introduced into sh2a-or-sh3e 208 fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} 209 210 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e 211 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e 212 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 213 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 214 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 215 @@ -124,8 +124,8 @@ sh2a_or_sh3e: 216 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 217 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 218 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 219 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 220 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 221 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 222 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 223 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 224 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 225 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 226 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 227 --- a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2025-02-02 00:00:00.000000000 +0000 228 +++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2025-11-30 01:43:04.000000000 +0000 229 @@ -39,7 +39,7 @@ sh2a_or_sh4: 230 fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} 231 ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} 232 233 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e 234 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e 235 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 236 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 237 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 238 @@ -150,8 +150,8 @@ sh2a_or_sh4: 239 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 240 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 241 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 242 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 243 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 244 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 245 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 246 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 247 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 248 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 249 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh2a.s 250 --- a/gas/testsuite/gas/sh/arch/sh2a.s 2025-02-02 00:00:00.000000000 +0000 251 +++ b/gas/testsuite/gas/sh/arch/sh2a.s 2025-11-30 01:43:04.000000000 +0000 252 @@ -16,7 +16,7 @@ sh2a: 253 fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} 254 fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} 255 256 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e 257 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e 258 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 259 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 260 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 261 @@ -140,8 +140,8 @@ sh2a: 262 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 263 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 264 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 265 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 266 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 267 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 268 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 269 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 270 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 271 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 272 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh3-dsp.s 273 --- a/gas/testsuite/gas/sh/arch/sh3-dsp.s 2025-02-02 00:00:00.000000000 +0000 274 +++ b/gas/testsuite/gas/sh/arch/sh3-dsp.s 2025-11-30 01:43:04.000000000 +0000 275 @@ -12,7 +12,7 @@ 276 sh3_dsp: 277 ! Instructions introduced into sh3-dsp 278 279 -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu 280 +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu 281 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 282 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 283 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 284 @@ -152,8 +152,8 @@ sh3_dsp: 285 setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} 286 repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} 287 repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} 288 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 289 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 290 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 291 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 292 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 293 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 294 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 295 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh3-nommu.s 296 --- a/gas/testsuite/gas/sh/arch/sh3-nommu.s 2025-02-02 00:00:00.000000000 +0000 297 +++ b/gas/testsuite/gas/sh/arch/sh3-nommu.s 2025-11-30 01:43:04.000000000 +0000 298 @@ -26,7 +26,7 @@ sh3_nommu: 299 stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} 300 stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} 301 302 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu 303 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu 304 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 305 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 306 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 307 @@ -133,8 +133,8 @@ sh3_nommu: 308 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 309 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 310 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 311 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 312 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 313 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 314 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 315 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 316 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 317 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 318 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh3.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh3.s 319 --- a/gas/testsuite/gas/sh/arch/sh3.s 2025-02-02 00:00:00.000000000 +0000 320 +++ b/gas/testsuite/gas/sh/arch/sh3.s 2025-11-30 01:43:04.000000000 +0000 321 @@ -13,7 +13,7 @@ sh3: 322 ! Instructions introduced into sh3 323 ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} 324 325 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu 326 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu 327 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 328 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 329 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 330 @@ -128,8 +128,8 @@ sh3: 331 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 332 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 333 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 334 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 335 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 336 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 337 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 338 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 339 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 340 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 341 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh3e.s 342 --- a/gas/testsuite/gas/sh/arch/sh3e.s 2025-02-02 00:00:00.000000000 +0000 343 +++ b/gas/testsuite/gas/sh/arch/sh3e.s 2025-11-30 01:43:04.000000000 +0000 344 @@ -12,7 +12,7 @@ 345 sh3e: 346 ! Instructions introduced into sh3e 347 348 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu 349 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu 350 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 351 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 352 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 353 @@ -132,8 +132,8 @@ sh3e: 354 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 355 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 356 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 357 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 358 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 359 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 360 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 361 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 362 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 363 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 364 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh4-nofpu.s 365 --- a/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2025-02-02 00:00:00.000000000 +0000 366 +++ b/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2025-11-30 01:43:04.000000000 +0000 367 @@ -12,7 +12,7 @@ 368 sh4_nofpu: 369 ! Instructions introduced into sh4-nofpu 370 371 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu 372 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu 373 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 374 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 375 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 376 @@ -136,8 +136,8 @@ sh4_nofpu: 377 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 378 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 379 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 380 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 381 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 382 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 383 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 384 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 385 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 386 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 387 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 388 --- a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2025-02-02 00:00:00.000000000 +0000 389 +++ b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2025-11-30 01:43:04.000000000 +0000 390 @@ -24,7 +24,7 @@ sh4_nommu_nofpu: 391 stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} 392 stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} 393 394 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu 395 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu 396 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 397 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 398 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 399 @@ -139,8 +139,8 @@ sh4_nommu_nofpu: 400 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 401 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 402 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 403 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 404 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 405 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 406 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 407 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 408 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 409 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 410 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh4.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh4.s 411 --- a/gas/testsuite/gas/sh/arch/sh4.s 2025-02-02 00:00:00.000000000 +0000 412 +++ b/gas/testsuite/gas/sh/arch/sh4.s 2025-11-30 01:43:04.000000000 +0000 413 @@ -17,7 +17,7 @@ sh4: 414 fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} 415 ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} 416 417 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu 418 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu 419 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 420 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 421 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 422 @@ -145,8 +145,8 @@ sh4: 423 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 424 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 425 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 426 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 427 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 428 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 429 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 430 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 431 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 432 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 433 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 434 --- a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2025-02-02 00:00:00.000000000 +0000 435 +++ b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2025-11-30 01:43:04.000000000 +0000 436 @@ -19,7 +19,7 @@ sh4a_nofpu: 437 prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} 438 synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} 439 440 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu 441 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu 442 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 443 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 444 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 445 @@ -143,8 +143,8 @@ sh4a_nofpu: 446 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 447 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 448 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 449 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 450 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 451 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 452 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 453 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 454 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 455 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 456 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh4a.s 457 --- a/gas/testsuite/gas/sh/arch/sh4a.s 2025-02-02 00:00:00.000000000 +0000 458 +++ b/gas/testsuite/gas/sh/arch/sh4a.s 2025-11-30 01:43:04.000000000 +0000 459 @@ -13,7 +13,7 @@ sh4a: 460 ! Instructions introduced into sh4a 461 fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} 462 463 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu 464 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu 465 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 466 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 467 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 468 @@ -147,8 +147,8 @@ sh4a: 469 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 470 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 471 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 472 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 473 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 474 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 475 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 476 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 477 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 478 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 479 diff -ru --no-dereference --show-c-function binutils-2.44/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.44-0004-s390x-pie-symbol-binding/gas/testsuite/gas/sh/arch/sh4al-dsp.s 480 --- a/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2025-02-02 00:00:00.000000000 +0000 481 +++ b/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2025-11-30 01:43:04.000000000 +0000 482 @@ -48,7 +48,7 @@ sh4al_dsp: 483 dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} 484 dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} 485 486 -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu 487 +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu 488 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 489 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 490 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 491 @@ -202,8 +202,8 @@ sh4al_dsp: 492 setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} 493 repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} 494 repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} 495 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 496 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 497 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 498 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 499 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 500 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 501 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 502 diff -ru --no-dereference --show-c-function binutils-2.44/include/elf/sh.h binutils-2.44-0004-s390x-pie-symbol-binding/include/elf/sh.h 503 --- a/include/elf/sh.h 2025-02-02 00:00:00.000000000 +0000 504 +++ b/include/elf/sh.h 2025-11-30 01:43:04.000000000 +0000 505 @@ -39,6 +39,7 @@ extern "C" { 506 #define EF_SH2E 11 507 #define EF_SH4A 12 508 #define EF_SH2A 13 509 +#define EF_SHJ2 14 510 511 #define EF_SH4_NOFPU 16 512 #define EF_SH4A_NOFPU 17 513 @@ -50,6 +51,7 @@ extern "C" { 514 #define EF_SH2A_SH3_NOFPU 22 515 #define EF_SH2A_SH4 23 516 #define EF_SH2A_SH3E 24 517 +#define EF_SH2A_SH3_SHJ2 25 518 519 /* This one can only mix in objects from other EF_SH5 objects. */ 520 #define EF_SH5 10 521 @@ -72,7 +74,8 @@ extern "C" { 522 /* EF_SH2E */ bfd_mach_sh2e , \ 523 /* EF_SH4A */ bfd_mach_sh4a , \ 524 /* EF_SH2A */ bfd_mach_sh2a , \ 525 -/* 14, 15 */ 0, 0, \ 526 +/* EF_SHJ2 */ bfd_mach_shj2 , \ 527 +/* 15 */ 0, \ 528 /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ 529 /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ 530 /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ 531 @@ -81,7 +84,8 @@ extern "C" { 532 /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ 533 /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ 534 /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ 535 -/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e 536 +/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ 537 +/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 538 539 /* Convert arch_sh* into EF_SH*. */ 540 int sh_find_elf_flags (unsigned int arch_set); 541 diff -ru --no-dereference --show-c-function binutils-2.44/opcodes/sh-dis.c binutils-2.44-0004-s390x-pie-symbol-binding/opcodes/sh-dis.c 542 --- a/opcodes/sh-dis.c 2025-02-02 00:00:00.000000000 +0000 543 +++ b/opcodes/sh-dis.c 2025-11-30 01:43:04.000000000 +0000 544 @@ -866,6 +866,9 @@ print_insn_sh (bfd_vma memaddr, struct d 545 case XMTRX_M4: 546 fprintf_fn (stream, "xmtrx"); 547 break; 548 + case A_IND_0: 549 + fprintf_fn (stream, "@r0"); 550 + break; 551 default: 552 abort (); 553 } 554 diff -ru --no-dereference --show-c-function binutils-2.44/opcodes/sh-opc.h binutils-2.44-0004-s390x-pie-symbol-binding/opcodes/sh-opc.h 555 --- a/opcodes/sh-opc.h 2025-02-02 00:00:00.000000000 +0000 556 +++ b/opcodes/sh-opc.h 2025-11-30 01:43:04.000000000 +0000 557 @@ -192,7 +192,8 @@ typedef enum 558 FPUL_N, 559 FPUL_M, 560 FPSCR_N, 561 - FPSCR_M 562 + FPSCR_M, 563 + A_IND_0 564 } 565 sh_arg_type; 566 567 @@ -216,9 +217,11 @@ sh_dsp_reg_nums; 568 #define arch_sh4_base (1 << 5) 569 #define arch_sh4a_base (1 << 6) 570 #define arch_sh2a_base (1 << 7) 571 -#define arch_sh_base_mask MASK (0, 7) 572 +#define arch_shj2_base (1 << 8) 573 +#define arch_sh2a_sh3_shj2_base (1 << 9) 574 +#define arch_sh_base_mask MASK (0, 9) 575 576 -/* Bits 8 ... 24 are currently free. */ 577 +/* Bits 10 ... 24 are currently free. */ 578 579 /* This is an annotation on instruction types, but we 580 abuse the arch field in instructions to denote it. */ 581 @@ -256,6 +259,8 @@ sh_dsp_reg_nums; 582 #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) 583 #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) 584 #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) 585 +#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) 586 +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) 587 588 #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) 589 #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) 590 @@ -320,7 +325,8 @@ SH4AL-dsp 591 #define arch_sh2_up (arch_sh2 \ 592 | arch_sh2e_up \ 593 | arch_sh2a_nofpu_or_sh3_nommu_up \ 594 - | arch_sh_dsp_up) 595 + | arch_sh_dsp_up \ 596 + | arch_shj2_up) 597 #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ 598 | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ 599 | arch_sh2a_or_sh3e_up \ 600 @@ -346,6 +352,12 @@ SH4AL-dsp 601 #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ 602 | arch_sh4a_up \ 603 | arch_sh4al_dsp_up) 604 +#define arch_shj2_up ( arch_shj2) 605 +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ 606 + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ 607 + | arch_sh2a_or_sh3e_up \ 608 + | arch_sh3_nommu_up \ 609 + | arch_shj2_up) 610 611 /* Right branches. */ 612 #define arch_sh2e_up (arch_sh2e \ 613 @@ -714,9 +726,9 @@ const sh_opcode_info sh_table[] = 614 615 /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8S,HEX_8}, arch_sh_dsp_up}, 616 617 -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, 618 +/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, 619 620 -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, 621 +/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, 622 623 /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, 624 625 @@ -1194,7 +1206,7 @@ const sh_opcode_info sh_table[] = 626 {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, 627 /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ 628 {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, 629 - 630 + /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, 631 { 0, {0}, {0}, 0 } 632 }; 633