mcm-binutils-2.32-merged.diff (57567B)
1 diff -ru --no-dereference --show-c-function binutils-2.32/bfd/archures.c binutils-2.32-0005-sh-fdpic-pr31619/bfd/archures.c 2 --- a/bfd/archures.c 2019-01-19 16:01:32.000000000 +0000 3 +++ b/bfd/archures.c 2025-11-30 01:41:23.000000000 +0000 4 @@ -298,6 +298,8 @@ DESCRIPTION 5 .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 6 .#define bfd_mach_sh2a_or_sh4 0x2a3 7 .#define bfd_mach_sh2a_or_sh3e 0x2a4 8 +.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 9 +.#define bfd_mach_shj2 0x2c 10 .#define bfd_mach_sh2e 0x2e 11 .#define bfd_mach_sh3 0x30 12 .#define bfd_mach_sh3_nommu 0x31 13 diff -ru --no-dereference --show-c-function binutils-2.32/bfd/bfd-in2.h binutils-2.32-0005-sh-fdpic-pr31619/bfd/bfd-in2.h 14 --- a/bfd/bfd-in2.h 2019-01-19 16:01:32.000000000 +0000 15 +++ b/bfd/bfd-in2.h 2025-11-30 01:41:23.000000000 +0000 16 @@ -2197,6 +2197,8 @@ enum bfd_architecture 17 #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 18 #define bfd_mach_sh2a_or_sh4 0x2a3 19 #define bfd_mach_sh2a_or_sh3e 0x2a4 20 +#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 21 +#define bfd_mach_shj2 0x2c 22 #define bfd_mach_sh2e 0x2e 23 #define bfd_mach_sh3 0x30 24 #define bfd_mach_sh3_nommu 0x31 25 diff -ru --no-dereference --show-c-function binutils-2.32/bfd/cpu-sh.c binutils-2.32-0005-sh-fdpic-pr31619/bfd/cpu-sh.c 26 --- a/bfd/cpu-sh.c 2019-01-19 16:01:32.000000000 +0000 27 +++ b/bfd/cpu-sh.c 2025-11-30 01:41:23.000000000 +0000 28 @@ -43,7 +43,10 @@ 29 #define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16 30 #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17 31 #define SH2A_OR_SH4_NEXT arch_info_struct + 18 32 -#define SH2A_OR_SH3E_NEXT NULL 33 +#define SH2A_OR_SH3E_NEXT arch_info_struct + 19 34 +#define SHJ2_NEXT arch_info_struct + 20 35 +#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL 36 + 37 38 static const bfd_arch_info_type arch_info_struct[] = 39 { 40 @@ -332,6 +335,36 @@ static const bfd_arch_info_type arch_inf 41 bfd_arch_default_fill, 42 SH2A_OR_SH3E_NEXT 43 }, 44 + { 45 + 32, /* 32 bits in a word. */ 46 + 32, /* 32 bits in an address. */ 47 + 8, /* 8 bits in a byte. */ 48 + bfd_arch_sh, 49 + bfd_mach_shj2, 50 + "sh", /* Architecture name. . */ 51 + "j2", /* Machine name. */ 52 + 1, 53 + FALSE, /* Not the default. */ 54 + bfd_default_compatible, 55 + bfd_default_scan, 56 + bfd_arch_default_fill, 57 + SHJ2_NEXT 58 + }, 59 + { 60 + 32, /* 32 bits in a word. */ 61 + 32, /* 32 bits in an address. */ 62 + 8, /* 8 bits in a byte. */ 63 + bfd_arch_sh, 64 + bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, 65 + "sh", /* Architecture name. . */ 66 + "sh2a-or-sh3e-or-j2", /* Machine name. */ 67 + 1, 68 + FALSE, /* Not the default. */ 69 + bfd_default_compatible, 70 + bfd_default_scan, 71 + bfd_arch_default_fill, 72 + SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT 73 + }, 74 }; 75 76 const bfd_arch_info_type bfd_sh_arch = 77 @@ -382,6 +415,8 @@ static struct { unsigned long bfd_mach, 78 { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, 79 { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, 80 { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, 81 + { bfd_mach_shj2, arch_shj2, arch_shj2_up }, 82 + { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, 83 { 0, 0, 0 } /* Terminator. */ 84 }; 85 86 diff -ru --no-dereference --show-c-function binutils-2.32/bfd/elf32-arm.c binutils-2.32-0005-sh-fdpic-pr31619/bfd/elf32-arm.c 87 --- a/bfd/elf32-arm.c 2019-01-28 17:09:04.000000000 +0000 88 +++ b/bfd/elf32-arm.c 2025-11-30 01:41:43.000000000 +0000 89 @@ -4836,7 +4836,7 @@ elf32_arm_tls_transition (struct bfd_lin 90 { 91 int is_local = (h == NULL); 92 93 - if (bfd_link_pic (info) 94 + if (bfd_link_dll (info) 95 || (h && h->root.type == bfd_link_hash_undefweak)) 96 return r_type; 97 98 @@ -11499,8 +11499,7 @@ elf32_arm_final_link_relocate (reloc_how 99 if (dynreloc_st_type == STT_GNU_IFUNC) 100 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE); 101 else if (bfd_link_pic (info) 102 - && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT 103 - || h->root.type != bfd_link_hash_undefweak)) 104 + && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) 105 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE); 106 else 107 { 108 @@ -11624,7 +11623,7 @@ elf32_arm_final_link_relocate (reloc_how 109 { 110 /* If we don't know the module number, create a relocation 111 for it. */ 112 - if (bfd_link_pic (info)) 113 + if (bfd_link_dll (info)) 114 { 115 Elf_Internal_Rela outrel; 116 117 @@ -11728,7 +11727,7 @@ elf32_arm_final_link_relocate (reloc_how 118 now, and emit any relocations. If both an IE GOT and a 119 GD GOT are necessary, we emit the GD first. */ 120 121 - if ((bfd_link_pic (info) || indx != 0) 122 + if ((bfd_link_dll (info) || indx != 0) 123 && (h == NULL 124 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT 125 && !resolved_to_zero) 126 @@ -11745,7 +11744,7 @@ elf32_arm_final_link_relocate (reloc_how 127 /* We should have relaxed, unless this is an undefined 128 weak symbol. */ 129 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak)) 130 - || bfd_link_pic (info)); 131 + || bfd_link_dll (info)); 132 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8 133 <= globals->root.sgotplt->size); 134 135 @@ -11951,9 +11950,9 @@ elf32_arm_final_link_relocate (reloc_how 136 unsigned long data, insn; 137 unsigned thumb; 138 139 - data = bfd_get_32 (input_bfd, hit_data); 140 + data = bfd_get_signed_32 (input_bfd, hit_data); 141 thumb = data & 1; 142 - data &= ~1u; 143 + data &= ~1ul; 144 145 if (thumb) 146 { 147 @@ -16232,7 +16231,7 @@ allocate_dynrelocs_for_symbol (struct el 148 indx = h->dynindx; 149 150 if (tls_type != GOT_NORMAL 151 - && (bfd_link_pic (info) || indx != 0) 152 + && (bfd_link_dll (info) || indx != 0) 153 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT 154 || h->root.type != bfd_link_hash_undefweak)) 155 { 156 @@ -16268,8 +16267,7 @@ allocate_dynrelocs_for_symbol (struct el 157 GOT entry's R_ARM_IRELATIVE relocation. */ 158 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1); 159 else if (bfd_link_pic (info) 160 - && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT 161 - || h->root.type != bfd_link_hash_undefweak)) 162 + && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) 163 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */ 164 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1); 165 else if (htab->fdpic_p && tls_type == GOT_NORMAL) 166 diff -ru --no-dereference --show-c-function binutils-2.32/bfd/elf32-sh.c binutils-2.32-0005-sh-fdpic-pr31619/bfd/elf32-sh.c 167 --- a/bfd/elf32-sh.c 2019-01-19 16:01:33.000000000 +0000 168 +++ b/bfd/elf32-sh.c 2025-11-30 01:41:49.774985936 +0000 169 @@ -61,7 +61,7 @@ static bfd_vma tpoff 170 not. If the symbol is protected, we want the local address, but 171 its function descriptor must be assigned by the dynamic linker. */ 172 #define SYMBOL_FUNCDESC_LOCAL(INFO, H) \ 173 - (SYMBOL_REFERENCES_LOCAL (INFO, H) \ 174 + (!(H) || (H)->dynindx < 0 || (H)->forced_local \ 175 || ! elf_hash_table (INFO)->dynamic_sections_created) 176 177 #define SH_PARTIAL32 TRUE 178 @@ -4405,20 +4405,6 @@ sh_elf_relocate_section (bfd *output_bfd 179 /* Undefined weak symbol which will not be dynamically 180 resolved later; leave it at zero. */ 181 goto funcdesc_leave_zero; 182 - else if (SYMBOL_CALLS_LOCAL (info, h) 183 - && ! SYMBOL_FUNCDESC_LOCAL (info, h)) 184 - { 185 - /* If the symbol needs a non-local function descriptor 186 - but binds locally (i.e., its visibility is 187 - protected), emit a dynamic relocation decayed to 188 - section+offset. This is an optimization; the dynamic 189 - linker would resolve our function descriptor request 190 - to our copy of the function anyway. */ 191 - dynindx = elf_section_data (h->root.u.def.section 192 - ->output_section)->dynindx; 193 - relocation += h->root.u.def.section->output_offset 194 - + h->root.u.def.value; 195 - } 196 else if (! SYMBOL_FUNCDESC_LOCAL (info, h)) 197 { 198 /* If the symbol is dynamic and there will be dynamic 199 diff -ru --no-dereference --show-c-function binutils-2.32/binutils/readelf.c binutils-2.32-0005-sh-fdpic-pr31619/binutils/readelf.c 200 --- a/binutils/readelf.c 2019-01-19 16:01:33.000000000 +0000 201 +++ b/binutils/readelf.c 2025-11-30 01:41:23.000000000 +0000 202 @@ -3528,6 +3528,8 @@ get_machine_flags (Filedata * filedata, 203 case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break; 204 case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break; 205 case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break; 206 + case EF_SHJ2: strcat (buf, ", j2"); break; 207 + case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break; 208 default: strcat (buf, _(", unknown ISA")); break; 209 } 210 211 diff -ru --no-dereference --show-c-function binutils-2.32/gas/config/tc-sh.c binutils-2.32-0005-sh-fdpic-pr31619/gas/config/tc-sh.c 212 --- a/gas/config/tc-sh.c 2019-01-19 16:01:33.000000000 +0000 213 +++ b/gas/config/tc-sh.c 2025-11-30 01:41:23.000000000 +0000 214 @@ -1251,6 +1251,8 @@ get_operands (sh_opcode_info *info, char 215 ptr++; 216 } 217 get_operand (&ptr, operand + 2); 218 + if (strcmp (info->name,"cas") == 0) 219 + operand[2].type = A_IND_0; 220 } 221 else 222 { 223 @@ -1790,7 +1792,10 @@ get_specific (sh_opcode_info *opcode, sh 224 goto fail; 225 reg_m = 4; 226 break; 227 - 228 + case A_IND_0: 229 + if (user->reg != 0) 230 + goto fail; 231 + break; 232 default: 233 printf (_("unhandled %d\n"), arg); 234 goto fail; 235 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 236 --- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-01-19 16:01:33.000000000 +0000 237 +++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2025-11-30 01:41:23.000000000 +0000 238 @@ -12,8 +12,6 @@ 239 sh2a_nofpu_or_sh3_nommu: 240 ! Instructions introduced into sh2a-nofpu-or-sh3-nommu 241 pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} 242 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 243 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 244 245 ! Instructions inherited from ancestors: sh sh2 246 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 247 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 248 --- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-01-19 16:01:33.000000000 +0000 249 +++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2025-11-30 01:41:23.000000000 +0000 250 @@ -12,7 +12,7 @@ 251 sh2a_nofpu_or_sh4_nommu_nofpu: 252 ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu 253 254 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu 255 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu 256 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 257 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 258 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 259 @@ -119,8 +119,8 @@ sh2a_nofpu_or_sh4_nommu_nofpu: 260 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 261 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 262 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 263 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 264 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 265 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 266 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 267 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 268 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 269 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 270 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 271 --- a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-01-19 16:01:33.000000000 +0000 272 +++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2025-11-30 01:41:23.000000000 +0000 273 @@ -64,7 +64,7 @@ sh2a_nofpu: 274 movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} 275 movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} 276 277 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu 278 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu 279 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 280 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 281 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 282 @@ -171,8 +171,8 @@ sh2a_nofpu: 283 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 284 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 285 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 286 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 287 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 288 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 289 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 290 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 291 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 292 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 293 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 294 --- a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-01-19 16:01:33.000000000 +0000 295 +++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2025-11-30 01:41:23.000000000 +0000 296 @@ -13,7 +13,7 @@ sh2a_or_sh3e: 297 ! Instructions introduced into sh2a-or-sh3e 298 fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} 299 300 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e 301 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e 302 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 303 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 304 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 305 @@ -124,8 +124,8 @@ sh2a_or_sh3e: 306 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 307 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 308 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 309 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 310 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 311 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 312 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 313 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 314 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 315 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 316 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 317 --- a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-01-19 16:01:33.000000000 +0000 318 +++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2025-11-30 01:41:23.000000000 +0000 319 @@ -39,7 +39,7 @@ sh2a_or_sh4: 320 fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} 321 ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} 322 323 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e 324 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e 325 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 326 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 327 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 328 @@ -150,8 +150,8 @@ sh2a_or_sh4: 329 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 330 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 331 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 332 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 333 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 334 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 335 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 336 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 337 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 338 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 339 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh2a.s 340 --- a/gas/testsuite/gas/sh/arch/sh2a.s 2019-01-19 16:01:33.000000000 +0000 341 +++ b/gas/testsuite/gas/sh/arch/sh2a.s 2025-11-30 01:41:23.000000000 +0000 342 @@ -16,7 +16,7 @@ sh2a: 343 fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} 344 fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} 345 346 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e 347 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e 348 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 349 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 350 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 351 @@ -140,8 +140,8 @@ sh2a: 352 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 353 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 354 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 355 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 356 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 357 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 358 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 359 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 360 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 361 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 362 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh3-dsp.s 363 --- a/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-01-19 16:01:33.000000000 +0000 364 +++ b/gas/testsuite/gas/sh/arch/sh3-dsp.s 2025-11-30 01:41:23.000000000 +0000 365 @@ -12,7 +12,7 @@ 366 sh3_dsp: 367 ! Instructions introduced into sh3-dsp 368 369 -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu 370 +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu 371 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 372 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 373 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 374 @@ -152,8 +152,8 @@ sh3_dsp: 375 setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} 376 repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} 377 repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} 378 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 379 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 380 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 381 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 382 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 383 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 384 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 385 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh3-nommu.s 386 --- a/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-01-19 16:01:33.000000000 +0000 387 +++ b/gas/testsuite/gas/sh/arch/sh3-nommu.s 2025-11-30 01:41:23.000000000 +0000 388 @@ -26,7 +26,7 @@ sh3_nommu: 389 stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} 390 stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} 391 392 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu 393 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu 394 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 395 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 396 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 397 @@ -133,8 +133,8 @@ sh3_nommu: 398 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 399 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 400 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 401 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 402 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 403 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 404 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 405 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 406 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 407 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 408 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh3.s 409 --- a/gas/testsuite/gas/sh/arch/sh3.s 2019-01-19 16:01:33.000000000 +0000 410 +++ b/gas/testsuite/gas/sh/arch/sh3.s 2025-11-30 01:41:23.000000000 +0000 411 @@ -13,7 +13,7 @@ sh3: 412 ! Instructions introduced into sh3 413 ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} 414 415 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu 416 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu 417 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 418 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 419 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 420 @@ -128,8 +128,8 @@ sh3: 421 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 422 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 423 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 424 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 425 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 426 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 427 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 428 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 429 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 430 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 431 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh3e.s 432 --- a/gas/testsuite/gas/sh/arch/sh3e.s 2019-01-19 16:01:33.000000000 +0000 433 +++ b/gas/testsuite/gas/sh/arch/sh3e.s 2025-11-30 01:41:23.000000000 +0000 434 @@ -12,7 +12,7 @@ 435 sh3e: 436 ! Instructions introduced into sh3e 437 438 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu 439 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu 440 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 441 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 442 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 443 @@ -132,8 +132,8 @@ sh3e: 444 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 445 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 446 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 447 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 448 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 449 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 450 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 451 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 452 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 453 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 454 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh4-nofpu.s 455 --- a/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-01-19 16:01:33.000000000 +0000 456 +++ b/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2025-11-30 01:41:23.000000000 +0000 457 @@ -12,7 +12,7 @@ 458 sh4_nofpu: 459 ! Instructions introduced into sh4-nofpu 460 461 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu 462 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu 463 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 464 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 465 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 466 @@ -136,8 +136,8 @@ sh4_nofpu: 467 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 468 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 469 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 470 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 471 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 472 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 473 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 474 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 475 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 476 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 477 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 478 --- a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-01-19 16:01:33.000000000 +0000 479 +++ b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2025-11-30 01:41:23.000000000 +0000 480 @@ -24,7 +24,7 @@ sh4_nommu_nofpu: 481 stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} 482 stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} 483 484 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu 485 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu 486 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 487 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 488 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 489 @@ -139,8 +139,8 @@ sh4_nommu_nofpu: 490 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 491 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 492 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 493 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 494 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 495 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 496 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 497 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 498 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 499 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 500 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh4.s 501 --- a/gas/testsuite/gas/sh/arch/sh4.s 2019-01-19 16:01:33.000000000 +0000 502 +++ b/gas/testsuite/gas/sh/arch/sh4.s 2025-11-30 01:41:23.000000000 +0000 503 @@ -17,7 +17,7 @@ sh4: 504 fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} 505 ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} 506 507 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu 508 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu 509 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 510 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 511 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 512 @@ -145,8 +145,8 @@ sh4: 513 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 514 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 515 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 516 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 517 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 518 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 519 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 520 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 521 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 522 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 523 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 524 --- a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-01-19 16:01:33.000000000 +0000 525 +++ b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2025-11-30 01:41:23.000000000 +0000 526 @@ -19,7 +19,7 @@ sh4a_nofpu: 527 prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} 528 synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} 529 530 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu 531 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu 532 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 533 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 534 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 535 @@ -143,8 +143,8 @@ sh4a_nofpu: 536 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 537 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 538 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 539 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 540 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 541 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 542 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 543 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 544 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 545 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 546 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh4a.s 547 --- a/gas/testsuite/gas/sh/arch/sh4a.s 2019-01-19 16:01:33.000000000 +0000 548 +++ b/gas/testsuite/gas/sh/arch/sh4a.s 2025-11-30 01:41:23.000000000 +0000 549 @@ -13,7 +13,7 @@ sh4a: 550 ! Instructions introduced into sh4a 551 fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} 552 553 -! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu 554 +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu 555 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 556 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 557 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 558 @@ -147,8 +147,8 @@ sh4a: 559 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 560 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} 561 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 562 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 563 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 564 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 565 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 566 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 567 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 568 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 569 diff -ru --no-dereference --show-c-function binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.32-0005-sh-fdpic-pr31619/gas/testsuite/gas/sh/arch/sh4al-dsp.s 570 --- a/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-01-19 16:01:33.000000000 +0000 571 +++ b/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2025-11-30 01:41:23.000000000 +0000 572 @@ -48,7 +48,7 @@ sh4al_dsp: 573 dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} 574 dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} 575 576 -! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu 577 +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu 578 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} 579 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} 580 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} 581 @@ -202,8 +202,8 @@ sh4al_dsp: 582 setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} 583 repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} 584 repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} 585 - shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} 586 - shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} 587 + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 588 + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} 589 shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} 590 shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} 591 shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} 592 diff -ru --no-dereference --show-c-function binutils-2.32/include/elf/sh.h binutils-2.32-0005-sh-fdpic-pr31619/include/elf/sh.h 593 --- a/include/elf/sh.h 2019-01-19 16:01:33.000000000 +0000 594 +++ b/include/elf/sh.h 2025-11-30 01:41:23.000000000 +0000 595 @@ -39,6 +39,7 @@ extern "C" { 596 #define EF_SH2E 11 597 #define EF_SH4A 12 598 #define EF_SH2A 13 599 +#define EF_SHJ2 14 600 601 #define EF_SH4_NOFPU 16 602 #define EF_SH4A_NOFPU 17 603 @@ -50,6 +51,7 @@ extern "C" { 604 #define EF_SH2A_SH3_NOFPU 22 605 #define EF_SH2A_SH4 23 606 #define EF_SH2A_SH3E 24 607 +#define EF_SH2A_SH3_SHJ2 25 608 609 /* This one can only mix in objects from other EF_SH5 objects. */ 610 #define EF_SH5 10 611 @@ -72,7 +74,8 @@ extern "C" { 612 /* EF_SH2E */ bfd_mach_sh2e , \ 613 /* EF_SH4A */ bfd_mach_sh4a , \ 614 /* EF_SH2A */ bfd_mach_sh2a , \ 615 -/* 14, 15 */ 0, 0, \ 616 +/* EF_SHJ2 */ bfd_mach_shj2 , \ 617 +/* 15 */ 0, \ 618 /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ 619 /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ 620 /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ 621 @@ -81,7 +84,8 @@ extern "C" { 622 /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ 623 /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ 624 /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ 625 -/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e 626 +/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ 627 +/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 628 629 /* Convert arch_sh* into EF_SH*. */ 630 int sh_find_elf_flags (unsigned int arch_set); 631 diff -ru --no-dereference --show-c-function binutils-2.32/opcodes/sh-dis.c binutils-2.32-0005-sh-fdpic-pr31619/opcodes/sh-dis.c 632 --- a/opcodes/sh-dis.c 2019-01-19 16:01:34.000000000 +0000 633 +++ b/opcodes/sh-dis.c 2025-11-30 01:41:23.000000000 +0000 634 @@ -856,6 +856,9 @@ print_insn_sh (bfd_vma memaddr, struct d 635 case XMTRX_M4: 636 fprintf_fn (stream, "xmtrx"); 637 break; 638 + case A_IND_0: 639 + fprintf_fn (stream, "@r0"); 640 + break; 641 default: 642 abort (); 643 } 644 diff -ru --no-dereference --show-c-function binutils-2.32/opcodes/sh-opc.h binutils-2.32-0005-sh-fdpic-pr31619/opcodes/sh-opc.h 645 --- a/opcodes/sh-opc.h 2019-01-19 16:01:34.000000000 +0000 646 +++ b/opcodes/sh-opc.h 2025-11-30 01:41:23.000000000 +0000 647 @@ -191,7 +191,8 @@ typedef enum 648 FPUL_N, 649 FPUL_M, 650 FPSCR_N, 651 - FPSCR_M 652 + FPSCR_M, 653 + A_IND_0 654 } 655 sh_arg_type; 656 657 @@ -215,9 +216,11 @@ sh_dsp_reg_nums; 658 #define arch_sh4_base (1 << 5) 659 #define arch_sh4a_base (1 << 6) 660 #define arch_sh2a_base (1 << 7) 661 -#define arch_sh_base_mask MASK (0, 7) 662 +#define arch_shj2_base (1 << 8) 663 +#define arch_sh2a_sh3_shj2_base (1 << 9) 664 +#define arch_sh_base_mask MASK (0, 9) 665 666 -/* Bits 8 ... 24 are currently free. */ 667 +/* Bits 10 ... 24 are currently free. */ 668 669 /* This is an annotation on instruction types, but we 670 abuse the arch field in instructions to denote it. */ 671 @@ -255,6 +258,8 @@ sh_dsp_reg_nums; 672 #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) 673 #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) 674 #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) 675 +#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) 676 +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) 677 678 #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) 679 #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) 680 @@ -319,7 +324,8 @@ SH4AL-dsp 681 #define arch_sh2_up (arch_sh2 \ 682 | arch_sh2e_up \ 683 | arch_sh2a_nofpu_or_sh3_nommu_up \ 684 - | arch_sh_dsp_up) 685 + | arch_sh_dsp_up \ 686 + | arch_shj2_up) 687 #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ 688 | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ 689 | arch_sh2a_or_sh3e_up \ 690 @@ -345,6 +351,12 @@ SH4AL-dsp 691 #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ 692 | arch_sh4a_up \ 693 | arch_sh4al_dsp_up) 694 +#define arch_shj2_up ( arch_shj2) 695 +#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ 696 + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ 697 + | arch_sh2a_or_sh3e_up \ 698 + | arch_sh3_nommu_up \ 699 + | arch_shj2_up) 700 701 /* Right branches. */ 702 #define arch_sh2e_up (arch_sh2e \ 703 @@ -713,9 +725,9 @@ const sh_opcode_info sh_table[] = 704 705 /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, 706 707 -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, 708 +/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, 709 710 -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, 711 +/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, 712 713 /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, 714 715 @@ -1193,7 +1205,7 @@ const sh_opcode_info sh_table[] = 716 {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, 717 /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ 718 {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, 719 - 720 + /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, 721 { 0, {0}, {0}, 0 } 722 }; 723